As well known by those skilled in the art, complete dielectric insulation between one or more electronic semiconductor devices can be obtained by using dielectric trenches integrated on silicon-on-insulator SOI substrates, thus forming dielectrically insulated wells for integrating these devices therein.
In particular, SOI substrates comprise a buried oxide layer BOX for forming the vertical insulation of the dielectrically insulated well, with dielectric trenches forming the side insulation thereof. The continuity between the buried oxide layer (vertical insulation) and dielectric trenches (side insulation) ensures a complete dielectric insulation of the wells, and thus the devices integrated therein.
With reference to FIG. 1, an integrated structure 1 comprising a dielectrically insulated well 2 formed according to known criteria will now be described. In particular, the integrated structure 1 comprises a substrate 3 whereon a buried oxide layer BOX 4 is formed. The BOX 4 forms the horizontal dielectric insulation of the dielectrically insulated well 2. In particular, the dielectrically insulated well 2 is formed in a silicon layer 5, defined as silicon-on-insulator or SOI, by dielectric trenches 6 that form a side insulation region 7 of the dielectrically insulated well 2. The dielectric trenches 6 also define a horizontal insulation region 8 corresponding to the buried oxide layer BOX 4 area between the dielectric trenches 6.
Side and horizontal insulation regions 7 and 8 define an inner integration area 9 wherein several types of components can be integrated. These components are to be insulated. The substrate 3 serves as a mechanical support during the manufacturing steps of the components to be integrated in the dielectrically insulated well 2.
This type of integrated structure, though advantageous with respect to the insulation of devices for low power applications, does not allow vertical-current-flow power devices, i.e., those devices having conduction paths starting from the surface of the integrated structure 1 and reaching the substrate 3, to be integrated because of the presence of the buried oxide layer 4. The buried oxide layer 4 prevents these conduction paths from being created.
Moreover, technologies for integrating electronic devices using this type of dielectrically insulated wells are more expensive than technologies for integrating electronic devices on traditional substrates because of the high production cost of an SOI substrate. Other types of dielectric insulation structures are also known, which can be formed at low production costs and which can have vertical-current-flow power devices integrated therein. An integrated structure is described, for example, in European Patent Application No. 1,043,769, which was published on Nov. 10, 2000, and is assigned to the current assignee of the present invention.
In particular, this European patent application describes a dielectric insulation structure formed by chemical etching of silicon regions to conveniently empty these regions, and obtain a structure 10 of the type shown in FIGS. 2A to 2D. With reference to FIG. 2A, the structure 10 is formed in a silicon layer 11, and comprises a dielectric trench structure 12 connected to a dielectric area 13 surrounding first and second hollow regions 14, 15. The dielectric trench structure 12 and the dielectric area 13 also define. an insulation well 16, wherein several types of electronic components can be integrated therein.
The insulation well 16 is obtained by forming at first the dielectric trench structure 12, and afterwards, hollow regions 14 and 15. In particular, the dielectric trenches 12 are formed through dry anisotropic etching according to known criteria, while the hollow regions 14 and 15 are obtained through dry or acid-solution isotropic etching. During the formation of the hollow regions 14 and 15, the walls of the dielectric trenches 12 are protected with dielectric material which is selective to silicon etching when forming the hollow regions. Afterwards, an oxidation process allows the hollow regions 14 and 15 to be dielectrically insulated, which forms the dielectric area 13, and thus the insulation well 16. A deposition process of a not very conductive material allows structure 12 to have dielectric trenches that are filled, and depending on the depth of the trench, the hallow regions 14 and 15 may also be filled.
A surface planarizing step completes formation of the structure 10. The structure 10 thus comprises an insulation well 16 dielectrically insulated from the residual silicon making up the structure 10, and wherein it is possible to integrate elementary components, and vertical conduction silicon regions such as the region 17.
It is thus possible, by using the prior art structure 10, to integrate insulation wells in a dedicated way, while keeping on the same chip regions for integrating power devices. Moreover, the structure 10 comprising the insulation well 16 has been obtained by using traditional, low-cost integration processes.
Though advantageous under many aspects, the above described structure 20 has structural problems concerning the three-dimensional construction of the insulation well 16. In particular, during the formation of the hollow regions 14 and 15, the silicon portion forming the insulation well 16 must be mechanically supported to prevent it from breaking down.
FIGS. 2B, 2C and 2D schematically show supporting techniques of the insulation well 16 to be used to form the prior art structure 10. In particular, FIGS. 2B and 2C show mechanical supports 18 and 20 along a cross-dimensional view of the structure 10, while FIG. 2D shows a vertical mechanical support 23 starting from the bulk region of the structure 10.
In particular, the mechanical transversal support 18 of FIG. 2B for the insulation well 16 comprises an oxide region 19 serving as a side support of the insulation well 16. Actually, the approach shown in FIG. 2B does not allow a complete dielectric insulation because of the limited depth that can be obtained with the oxide region 19 of the mechanical transversal support 18 with respect to the dielectric trenches 12.
To remove this drawback, FIG. 2C shows a mechanical transversal support 20 comprising an oxide region 21 transversal to the structure 10, and an additional dielectric trench 22 integrated in a cross-direction of the structure 10. In this case, a complete dielectric insulation is obtained, but a double trench integration is introduced. Further process steps are thus required (particularly the addition of photomasking, etching, oxidizing, filling and planarizing steps), which make the process sequence more complicated.
It is also possible to obtain a complete dielectric insulation of the insulation well 16 by etching to form the hollow regions 14 and 15 while leaving therebetween a region that is a thin silicon portion 24 which serves also as a vertical mechanical support 23 of the insulation well 16. The silicon portion 24 must necessarily be sufficiently thin so that an oxidizing step to form the dielectric area 13 (dielectric insulation of hollow regions 14 and 15) completely oxidizes also this silicon portion 24.
In this case, the formation of the insulation well 16 requires a precise calibration of the etching process (both dry and in acid solution) and it is quite critical from a manufacturing point of view since the silicon portion 24 must not be excessively wide so as to be completely oxidized, and not too thin (or even void) so as to be able to mechanically support the insulation well 16. The oxidation of the silicon portion 24 of the support structure 23 causes also the overhanging insulation well 16 to be increased, thus negatively affecting the surface planarity of the structure 10.